Semiconductor device including an insulated gate field effect transistor and method of manufacting the same

ABSTRACT

A semiconductor device is disclosed including an IGFET (insulated gate field effect transistor) and a method of manufacturing the same. The semiconductor device may include an oxide film ( 115 ) or a nitride film ( 106 ) provided on a side surface of a gate electrode in such a manner that an overhang condition may not occur. In this way, operating characteristics of the IGFET may not be deteriorated and voids may not appear in filling regions of an interlayer insulating film so that isolation characteristics may not be deteriorated.

TECHNICAL FIELD

[0001] The present invention relates generally to a semiconductor deviceand method for manufacturing the same, and more specifically to asemiconductor device including an insulated gate field effect transistor(IGFET) including a gate electrode that includes polysilicon and metalor metal silicide having a high melting point and a method ofmanufacturing the same.

BACKGROUND OF THE INVENTION

[0002] In order to improve the integration of a semiconductor device itis desirable to make smaller contact holes for a contact electrode toprovide a connection between wiring layers and source/drain regions of ametal oxide semiconductor field effect transistor (MOSFET). It is alsodesirable to make the contact holes having improved accuracy ofplacement. In order to do this, a technique for forming a contact holeand electrode has been developed and is known as a self aligned contact(SAC).

[0003] Referring to FIGS. 9 and 10, cross-sectional views of aconventional manufacturing method of conventional semiconductor devicehaving SAC technique after various processing steps are set forth.

[0004] Referring now to FIG. 9(a), gate insulating film 202 consistingof silicon oxide (such as SiO₂) is formed on the surface of siliconsubstrate 201. A laminated film consists of poysilicon film 203, WSi(tungsten silicide) film 204, and a cap film 205 consisting of a siliconnitride (such as Si₃N₄) film. Using a photolithography technique, capfilm 205, WSi film 204, and polysilicon film 203 are etched into adesired pattern to form gate electrode 200.

[0005] In regions other than the gate electrode, the surface of gateinsulating film 202 is also etched and made thinner. Thus, the filmthickness of gate insulating film 202 is increased by thermal oxidationto replace the etched portions. As illustrated in FIG. 9(b), during thisstep, a silicon oxide side wall film 207 is formed on the side surfaceof gate electrode 200.

[0006] As illustrated in FIG. 9(c), the surface of silicon substrate issubjected to ion implantion with an impurity to form source drainregions 208 with a self alignment method in which gate electrode 200 isused as a mask. In this way, a MOS type transistor is formed.

[0007] Referring now to FIG. 9(d), silicon nitride film 209 is formedwith a chemical vapor deposition (CVD) method. Silicon nitride film 209serves as an etching stopper film.

[0008] Referring now to FIG. 10(a), interlayer insulating film 210 suchas a BPSG (Boro-PhosphoSilicate Glass) film is formed on the entiresurface to cover gate electrode and provide a flat surface.

[0009] Referring to FIG. 10(b), a hole 212 a is opened in interlayerinsulating film 210 over the source/drain region 208 using aphotolithography technique. When forming hole 212 a, etching stopperfilm 209 formed on the side surface of gate electrode 200 is not etched.Only interlayer insulating film 210 composed of BPSG is etched based ona difference of a selective etching ratio between etching stopper film209 and interlayer insulating film 210.

[0010] Referring now to FIG. 10(c), an anisotropic etching is applied toetching stopper film 209 exposed in hole 201 a. Further etching isapplied to gate insulating film 202. In this way, contact hole 212 isopened with a SAC technique.

[0011] Next, as illustrated in FIG. 10(d), a wiring electrode 213 a isformed in contact hole 212 to provide an electrical connection between atop part of wiring electrode 213 and source/drain region 208. Becausecontact hole 212 is formed using a SAC technique with etching stopperfilm 209 on the side surface of gate electrode 200, the MOS type elementcan be made fine. Even if a mask for opening a contact hole is out ofposition, side wall film 207 is not etched due to the etching stopperfilm 209. Thus, upper layer electrode 204 and lower layer electrode 203of gate electrode 200 can be prevented from being exposed in contacthole 212. Thus, a margin for positioning the mask for the contact hole212 can be increased and yield may be improved.

[0012]FIG. 11 are cross-sectional views of a conventional manufacturingmethod of conventional semiconductor device having SAC technique aftervarious processing steps are set forth. FIG. 11(a) illustrates a reduceddistance between the stopper film 209 and the surface of the siliconsubstrate 201 in a region close to the edge of lower layer electrode203. FIG. 11(b) illustrates an overhang in a side wall oxide layer. FIG.11(c) illustrates a void in a BPSG interlayer insulating film.

[0013] In the formation of a contact electrode using the conventionalSAC technology, a thermal oxidation step is performed as illustrated inFIG. 9(b). This thermal oxidation step is necessary because the gateinsulating film 202 is partially etched and made thinner during theetching of cap film 205, upper layer electrode 204, and lower layerelectrode 203 when forming the gate electrode 200. If the siliconnitride film (stopper film 209) is formed after the above-mentionedetching step without the additional thermal oxidation step, a distancebetween the stopper film 209 and the surface of the silicon substrate201 in a region close to the edge of lower layer electrode 203 isreduced. This reduced distance is illustrated in FIG. 11(a) as a reducedinterval t. Hot carriers are likely to be trapped in an interfacebetween the silicon nitride film (stopper film 209) and the siliconoxide film (gate insulating film 202). This can change the value of thethreshold voltage of the MOS type transistor, thus making it difficultto manufacture a MOS type transistor in accordance to the designedvalues. To solve this problem, the thermal oxidation step is performedas illustrate in FIG. 9(b) and the thickness of gate insulating film 202is increased. This may prevent variations of the threshold value causedby hot carriers being trapped in the interface between the siliconnitride film (stopper film 209) and the silicon oxide film (gateinsulating film 202) so that the desired characteristics of the MOStransistor can be achieved.

[0014] A technique of thermal oxidation including the side surface ofthe gate electrode has been proposed by the applicant and disclosed inJapanese Laid-Open Patent Publication No. 02-47871.

[0015] Thermal oxidation treatment for increasing the thickness of gateinsulating film 202 causes side surfaces of the polysilicon film (lowerlayer electrode 203) and the WSi film (upper layer electrode 204) to beoxidized simultaneously. In this way, silicon oxide film (side wall film207) is formed as illustrated in FIG. 9(b).

[0016] However, a silicide material, such as WSi (upper layer electrode204) may be more likely to be oxidized than polysilicon (lower layerelectrode 203) depending on the oxidation condition. Accordingly,depending upon the oxidation condition in the step illustrated in FIG.9(b), side wall film 207 may become thicker on the side surface of upperlayer electrode 204 than on the side surface of lower layer electrode203 as illustrated with side wall film 207 in FIG. 11(b). In this case,side wall film 207 may include an overhang portion 207 a that protrudeslaterally from upper layer electrode 204.

[0017] When there is an overhang portion 207 a protruding from a sidewall film 207, the regions around the sides of gate electrode 200 areshielded during the ion implantation step as illustrated in FIG. 11(b).This can prevent regions of the source/drain region 208 near the edgesof the gate electrode 200 from being sufficiently ion implanted with animpurity. This can cause an increased diffusion layer resistance of thesource/drain region 208 located in the vicinity of the gate electrode200 and adversely affect characteristics of the MOS transistor.

[0018] Also, a side wall film 207 including an overhang portion 207 a onthe side surface of upper layer electrode 204 can cause the CVD siliconnitride film (etching stopper film 209) in FIG. 9(d) to include aprotruding portion 209 a as illustrated in FIG. 11(c). Thus, when BPSGinterlayer insulating film 210 is formed, the protruding portion 209 acan make it difficult to fill the central region of the contact hole anda void X is likely to be formed as illustrated in FIG. 11(c). If thevoid X is formed in interlayer insulating film 210, a short-circuit canoccur in adjacent contact holes (such as contact hole 212 in FIG. 10(c))during the contact forming process. This reduces the yield of theproduct and increases manufacturing costs.

[0019] In light of the above discussion, it would be desirable toprovide a semiconductor device, which may include a side wall film, suchas a silicon oxide film or silicon nitride film, on the side surface ofa gate electrode that may not have an overhang portion. It would also bedesirable to provide an insulated gate field effect transistor (IGFET)that does not have characteristics affected by an overhang portion of aside wall film. It would also be desirable to provide a manufacturingmethod for the semiconductor device.

SUMMARY OF THE INVENTION

[0020] A semiconductor device according to the present embodiments mayinclude an IGFET (insulated gate field effect transistor) and a methodof manufacturing the same. The semiconductor device may include an oxidefilm or a nitride film provided on a side surface of a gate electrode insuch a manner than an overhang condition may not occur. In this way,operating characteristics of the IGFET may not be deteriorated and voidsmay not appear in filling regions of an interlayer insulating film sothat isolation characteristics may not be deteriorated.

[0021] According to one aspect of the embodiments, a semiconductordevice may include an IGFET including a gate electrode that may includea lower layer electrode formed on a gate insulating film and an upperlayer electrode formed on the lower layer electrode. A cap film may beformed on the upper layer electrode. A first nitride film may be formedon a side surface of the upper layer electrode. An oxide film may beformed on a side surface of the lower layer electrode. An etchingstopper film may include a second nitride film formed on the outside ofthe first nitride film and oxide film.

[0022] According to another aspect of the embodiments, the first nitridefilm may be a thermal nitride film.

[0023] According to another aspect of the embodiments, the first nitridefilm may be a rapidly heated thermal nitride film.

[0024] According to another aspect of the embodiments, the first nitridefilm may have a thickness of approximately 2 to 5 nm.

[0025] According to another aspect of the embodiments, an interlayerinsulating film may be formed to cover the gate electrode of the IGFET.A contact hole may be opened in the interlayer insulating film to exposea source/drain region of the IGFET. A conductor may fill the contacthole and be electrically connected with the source/drain region.

[0026] According to another aspect of the embodiments, the oxide filmmay be a thermal oxide film.

[0027] According to another aspect of the embodiments, the secondnitride film may be formed with chemical vapor deposition (CVD).

[0028] According to another aspect of the embodiments, a method formanufacturing a semiconductor device including an IGFET may include thesteps of forming a gate insulating film on a semiconductor substrate,forming a laminate film on the gate insulating film where the laminatefilm may include an insulating film formed on a second conductive filmformed on a first conductive film, etching the insulating film and thesecond conductive film into a predetermined pattern to form a cap filmand an upper layer gate electrode, forming a first nitride film on theside surface of the upper layer gate electrode, etching the firstconductive film using the cap layer, upper layer gate electrode and thenitride film as a mask to form a lower layer gate electrode, forming afirst oxide film on the side surface of the lower layer electrode, andforming an etching stopper film including a second nitride film over theentire surface.

[0029] According to another aspect of the embodiments, the firstconductive film may be a polysilicon film and the second conductive filmmay be a metal film.

[0030] According to another aspect of the embodiments, the firstconductive film may include a polysilicon film and the second conductivefilm may include a metal silicide film having a high melting point.

[0031] According to another aspect of the embodiments, the first nitridefilm may be a thermal nitride film and the first oxide film may be athermal oxide film.

[0032] According to another aspect of the embodiments, forming theetching stopper film may include forming the second nitride film with achemical vapor dposition.

[0033] According to another aspect of the embodiments, the first nitridefilm may be a thermal nitride film formed with a rapid thermalnitridation step using a lamp as a heat source.

[0034] According to another aspect of the embodiments, a method formanufacturing the semiconductor device may include the steps of forminga source/drain region by doping an impurity into the semiconductorsubstrate after the step of forming the first oxide film and forming aninterlayer insulating film over the entire surface and selectivelyetching the interlayer insulating film with a selective etching ratiofor the etching stopper film to open a contact hole after the step offorming the etching stopper film.

[0035] According to another aspect of the embodiments, a method formanufacturing the semiconductor device may include the steps of forminga lightly doped drain (LDD) region by doping a first impurityconcentration into the semiconductor substrate after the step of formingthe first oxide film, anisotropic etching the etching stopper film toform a side wall etching stopper film on side surfaces of the lowerlayer gate electrode, upper layer gate electrode, and cap layer, andforming a source/drain region by doping a second impurity concentrationinto the semiconductor substrate using the side wall etching stopperfilm as a mask. The first impurity concentration may be lower than thesecond impurity concentration.

[0036] According to another aspect of the embodiments, a method formanufacturing the semiconductor device may include the steps of forminga second oxide film over the entire surface of the substrate with achemical vapor deposition method, anisotropic etching the second oxidefilm to form a side oxide film on the side surface of the etchingstopper film, and forming the source/drain region after the step offorming the side wall.

[0037] According to another aspect of the embodiments, a semiconductordevice may include a first region and a second region. A first gateelectrode of a first IGFET in the first region may have a first lowerlayer electrode formed on a first gate insulating film and a first upperlayer electrode formed on the first lower layer electrode. A first capfilm may be formed on the first upper layer electrode. A first nitridefilm may be formed on a side surface of the first upper layer electrode.A first oxide film may be formed on a side surface of the first lowerlayer electrode. A first etching stopper film may include a secondnitride film formed on the outside of the first nitride film and firstoxide film. A second gate electrode of a second IGFET in the secondregion may have a second lower layer electrode formed on a second gateinsulating film and a second upper layer electrode formed on the secondlower layer electrode. A second cap film may be formed on the secondupper layer electrode. A third nitride film may be formed on a sidesurface of the second upper layer electrode. A second oxide film may beformed on a side surface of the second lower layer electrode. A secondetching stopper film may include a fourth nitride film formed on theoutside of the third nitride film and second oxide film. The first IGFETmay include a lightly doped drain.

[0038] According to another aspect of the embodiments, the semiconductordevice may be a semiconductor memory device.

[0039] According to another aspect of the embodiments, the first regionmay be a memory cell region and the second region may be a peripheralcircuit region.

[0040] According to another aspect of the embodiments, a first contactmay provide an electrical connection to a first sour/drain region of thefirst IGFET. A second contact may provide an electrical connection to asecond source/drain region of the second IGFET. A first spacing from thefirst contact to the first electrode may be greater than a secondspacing from the second contact to the second gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041]FIG. 1 is cross-sectional views of a semiconductor deviceaccording to a first embodiment after various processing steps.

[0042]FIG. 2 is cross-sectional views of a semiconductor deviceaccording to a first embodiment after various processing steps.

[0043]FIG. 3 is cross-sectional views of a semiconductor deviceaccording to a first embodiment after various processing steps.

[0044]FIG. 4 is cross-sectional views of a semiconductor deviceaccording to a second embodiment after various processing steps.

[0045]FIG. 5 is cross-sectional views of a semiconductor deviceaccording to a second embodiment after various processing steps.

[0046]FIG. 6 is cross-sectional views of a semiconductor deviceaccording to a second embodiment after various processing steps.

[0047]FIG. 7 is cross-sectional views of a semiconductor deviceaccording to a third embodiment after various processing steps.

[0048]FIG. 8 is cross-sectional views of a semiconductor deviceaccording to a third embodiment after various processing steps.

[0049]FIG. 9 is cross-sectional views of a conventional manufacturingmethod of conventional semiconductor device having SAC technique aftervarious processing steps.

[0050]FIG. 10 is cross-sectional views of a conventional manufacturingmethod of conventional semiconductor device having SAC technique aftervarious processing steps.

[0051]FIG. 11 is cross-sectional views of a conventional manufacturingmethod of conventional semiconductor device having SAC technique aftervarious processing steps.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] Various embodiments of the present invention will now bedescribed in detail with reference to a number of drawings.

[0053] FIGS. 1 to 3 are cross-sectional views of a semiconductor deviceaccording to a first embodiment after various processing steps.

[0054] Referring now to FIG. 1(a), the surface of a silicon substrate101 may be thermally oxidized to form silicon oxide film 102 (such asSiO₂). Silicon oxide film 102 may have a film thickness of approximately10 nm and may be used as a gate insulating film. Then, polisilicon film103 may be formed on the silicon oxide film 102 with a low pressurechemical vapor deposition (LPVD) method. Polysilicon film 103 may have athickness of approximately 100 nm. A WSi film (tungsten silicide film)104 may then be formed on the polysilicon film 103 with a CVD method.WSi film 104 may have a thickness of approximately 150 nm. Then siliconnitride film (such as Si₃N₄) 105 may be formed on the WSi film 104 witha sputtering method or a CVD method. Silicon nitride film 105 may have athickness of about 100 nm.

[0055] Referring now to FIG. 1(b), a mask including photoresist (notshown) may be formed on the silicon nitride film 105 and silicon nitridefilm 105. WSi film 104 may be etched into a desired pattern using themask. In this way, cap film 105 and upper layer electrode 104 may beformed. Upper layer electrode 104 may form a portion of a gateelectrode.

[0056] After the mask is removed, a RTN (Rapid Thermal Nitridation)process may be performed as illustrated in FIG. 1(c). The RTN processmay be performed using a lamp as a heat source. In this way, a sideanti-oxidizing film 106 may be formed on the side surface of upper layerelectrode 104. Side anti-oxidizing film 106 may be a silicon nitridefilm and may have a thickness of approximately 2-5 nm. A thin RTNsilicon nitride film (not shown) may also be formed on the surface ofthe exposed polysilicon film 103. Conditions of RTN may include ammonia(NH₃) gas flow rate of 5 to 10 (liters/minute) at 800 to 1000° C. for 30to 120 seconds, for example.

[0057] Referring now to FIG. 2(a), polysilicon film 103 may be etched inself-alignment with respect to cap film 105, upper layer electrode 104,and side surface anti-oxidizing film 106. The RTN silicon nitride filmon the upper surface of polysilicon film 103 may be etched and removedat the same time by a method such as anisotropic RE (reactive ion etch),while cap film 105 and anti-oxidizing film 106 on the side surface ofupper layer electrode 104 may not be etched. Also, polysilicon film 103may remain behind under the upper layer electrode 104 and sideanti-oxidizing film 106 to form lower layer electrode 103. In this way,a gate electrode 100 may be formed including cap film 105, upper layerelectrode 104, and lower layer electrode 103. The surface of gateinsulating film 102 may be etched to reduce the film thickness in aregion other than under the lower layer electrode 103.

[0058] Referring now to FIG. 2(b), a RTO (Rapid Thermal Oxidation)process may be performed to oxidize the side surface of lower electrode103 and the surface of gate insulating film 102 to form side oxidationfilm 107. The RTO process may use a lamp as a heat source. Sideoxidation film 107 may have a thickness of approximately 5 nm on theside surface of lower layer electrode 103. Gate insulating film 102 mayreturn to essentially its initial film thickness of approximately 10 nm.Conditions of RTO may include an oxygen (02) gas flow rate of 5 to 10(liters/minute) at 900 to 1100° C. for 30 to 120 seconds, for example.Silicon nitride cap film 105 may be formed on the upper surface of upperlayer electrode 104 and RTN silicon nitride anti-oxidizing film 106 maybe formed on the side surface of upper layer electrode 104 so that theupper surface and side surface of upper layer electrode 104 may beprevented from being oxidized. Thus, a thick silicon oxide film may notbe formed on the side surface. Even if upper layer electrode 104 isoxidized, silicon oxide film formed here may be so thin that it may beignored as compared with anti-oxidizing film 106. In this way, gateelectrode 100 may be formed with the above-mentioned process.

[0059] Referring now to FIG. 2(c), the surface of silicon substrate 101may be ion implanted with an impurity at low concentration with aself-alignment method using gate electrode 100 as a mask. In this way,source/drain regions 108 may be formed.

[0060] Referring now to FIG. 3(a), silicon nitride film 109 may beformed over the entire surface with a CVD method. Silicon nitride film109 may have a thickness of approximately 50 nm and may serve as anetching stopper film 109 covering the upper and side surfaces of gateelectrode 100.

[0061] Referring now to FIG. 3(b), an interlayer insulating film 110 maybe formed to cover and flatten the entire surface including gateelectrode 100. Interlayer insulating film 110 maybe a BPSG film. Then, amask 111 may be formed having an opening over a region corresponding toa source/drain region 108. Interlayer insulating film 110 may then beetched to form hole 112 a. When the forming of hole 112 a, a selectiveetching process for oxide film may be performed under conditions ofselective etching ratio of the BPSG as interlayer insulating film 110and CVD silicon nitride as etching stopper film 109. In this way, onlyinterlayer insulating film 110 may be etched without significantlyetching the etching stopper film 109.

[0062] Referring now to FIG. 3(c), stopper film 109 is etched at abottom surface of hole 112 a. Only etching stopper film 109 exposed at abottom surface of hole 112 a may be etched by using an anisotropicetching process for a nitride film. Also, gate insulating film 102comprising silicon oxide under the etching stopper film 109 at thebottom surface of hole 112 a may be etched with an etching process foroxide film. In this way, contact hole 112 may be formed with a SACmethod and silicon substrate 101 including source/drain region 108 maybe exposed. Accordingly, with the SAC method, even if the opening inmask 111 may be overlapped on gate electrode 100, upper and lower layerelectrodes (104 and 103) may be prevented from being exposed in contacthole 112 during the formation of contact hole 112.

[0063] Referring now to FIG. 3(d), polysilicon doped with an impuritymay be formed on interlayer insulating film 110 including contact hole112. Polysilicon may be patterned and etched with a mask (not shown) toform a wiring electrode 113. Wiring electrode 113 may include a contactelectrode 113 a formed in contact hole 112. In this way, contactelectrode 113 a may provide an electrical connection between sourcedrain/region 108 of an insulated gate field effect transistor (IGFET)and wiring electrode 113. The IGFET formed may be a metal oxidesemiconductor field effect transistor (MOSFET), as just one example.

[0064] In the semiconductor device including an IGFET formed asmentioned above, during the formation of gate electrode 100, upper layerelectrode 104 may be first formed, anti-oxidizing film 106 includingsilicon nitride may be formed on the side surface of upper layerelectrode 104 with RTN, then lower layer electrode 103 may be formed byself-alignment with upper layer electrode 104 and anti-oxidizing film106. Side surface oxide film 107 may be formed on the side surface oflower layer electrode 103 with RTO while the thickness of gateinsulating film 102 may be returned to approximately an initialthickness. Thus, side surface oxide film 107 on the side surface oflower layer electrode 103 may protrude from the side of lower layerelectrode 103 by its own thickness farther than anti-oxidizing film 106from the side surface of upper layer electrode 104. Because the sidesurface of upper layer electrode 104 may be covered with anti-oxidizingfilm 106, the side surface of upper layer electrode may not be oxidizedduring the RTO. In this way, the overhang state in which the sidesurface of upper layer electrode 104 protrudes beyond the side surfaceof lower layer electrode 103 may be prevented.

[0065] Accordingly, when source/drain region 108 is formed by ionimplantation of impurity under self-alignment with the upper layerelectrode 104, lower layer electrode 103, and antioxidizing film 106and/or side surface oxide film 107, no portion of the desiredsource/drain region 108 in the vicinity of the gate electrode may beshielded so that ions may be prevented from being implanted. Thus, theimpurity diffusion resistance of the source/drain region 108 in thevicinity of gate electrode may be prevented from increasing. Also, whenBPSG interlayer insulating film 110 is formed after CVD silicon nitrideetching stopper film 109 that covers gate electrode 100 is formed, avoid may not occur in a region close to the gate electrode 100. Evenwhen contact hole 112 and contact electrode 113 a are formed, wiringisolation properties of interlayer insulating film 110 may be preventedfrom suffering adverse affects due to unwanted voids in filling regions.In this way, characteristics of the IGFET formed may be prevented frombeing adversely affected.

[0066] Although in the aforementioned embodiment cap film 105 may beformed with a silicon nitride film, it may also be formed with a siliconoxide film, as just one example. Even if cap film 105 is formed with asilicon oxide film, etching stopper film 109 including the CVD siliconnitride film may be formed on cap film 105. Thus, cap film 105 may beprevented from being etched even if mask 111 is out of position whenetching to open contact hole 112 in interlayer insulating film 110.Hence, upper layer electrode 104 may be prevented from being exposed incontact hole 112.

[0067] A second embodiment of the present invention will now bedescribed with reference to FIGS. 4 to 6. The second embodiment is anexample where the present invention may be applied to a lightly dopeddrain (LDD) structure IGFET. Constituents in the second embodiment thatare similar to constituents in the first embodiment may be given thesame general reference character.

[0068] FIGS. 4 to 6 are cross-sectional views of a semiconductor deviceaccording to a second embodiment after various processing steps.

[0069] Referring now to FIG. 4(a), gate insulating film 102, polysiliconfilm 103, WSi film 104, and silicon nitride film 105 may be formed onthe surface of a silicon substrate 101 in a similar manner as the firstembodiment. Silicon nitride film 105 and WSi film 104 may be etched intoa predetermined pattern to form cap film 105 and upper layer electrode104 of a gate electrode.

[0070] Referring now to FIG. 4(b), a furnace nitriding (FN) process maybe performed to form anti-oxidizing film 106. Anti-oxidizing film mayinclude a silicon nitride film having a thickness of approximately 5 nmon the side surface of upper layer electrode 104. Anti-oxidizing film106 may be formed so that the FN silicon nitride film may be thinner onthe surface of polysilicon film 103 and side surface of cap film 105than on the side surface of upper layer electrode 104. Thus, the FNsilicon nitride film on the surface of polysilicon film 103 is notillustrated. Furnace nitriding conditions may include ammonia (NH₃) gasor nitrogen oxide (NO₂ or NO) with a flow rate of approximately 10(liters/minute) at approximately 800 to 1000° C. for approximately 5 to20 minutes, for example.

[0071] Referring now to FIG. 4(c), polysilicon film 103 may be etched inself-alignment with respect to cap film 105, upper layer electrode 104,and side surface anti-oxidizing film 106. The FN silicon nitride film onthe upper surface of polysilicon film 103 may be etched and removed atthe same time by a method such as anisotropic RIE (reactive ion etch),while cap film 105 and anti-oxidizing film 106 on the side surface ofupper layer electrode 104 may not be etched. Also, polysilicon film 103may remain behind under the upper layer electrode 104 and sideantioxidizing film 106 to form lower layer electrode 103. In this way, agate electrode 100 may be formed including cap film 105, upper layerelectrode 104, and lower layer electrode 103. The surface of gateinsulating film 102 may be etched to reduce the film thickness in aregion other than under the lower layer electrode 103.

[0072] Referring now to FIG. 5(a), the side surface of lower layerelectrode 103 and the surface of gate insulating film 102 may beoxidized with a furnace oxidizing process to form side surface oxidefilm 107. Also, gate insulating film 102 may be return to essentiallyits original thickness of about 10 nm. Conditions of furnace oxidizationmay include an oxygen (O₂) gas flow rate of approximately 5 to 10(liters/minute) at approximately 800 to 1000° C. for about 5 to 10seconds, for example. Silicon oxide cap film 105 may be formed on theupper surface of upper layer electrode 104 and FN silicon nitrideanti-oxidizing film 106 may be formed on the side surface of upper layerelectrode 104 so that the upper surface and side surface of upper layerelectrode 104 may be prevented from being oxidized. Thus, a thicksilicon oxide film may not be formed on the side surface. Even if upperlayer electrode 104 is oxidized, silicon oxide film formed here may beso thin that it may be ignored as compared with anti-oxidizing film 107.In this way, gate electrode 100 may be formed with the above-mentionedprocess.

[0073] Referring now to FIG. 5(b), the surface of silicon substrate 101may be ion implanted with an impurity at low concentration with aself-alignment method using gate electrode 100 as a mask. In this way,LDD regions 114 may be formed.

[0074] Referring now to FIG. 5(c), silicon nitride film 109 may beformed over the entire surface with a CVD method. Silicon nitride film109 may have a thickness of approximately 50 nm and may serve as anetching stopper film 109 covering the upper and side surfaces of gateelectrode 100. CVD silicon nitride film 109 may be subjected toanisotropic etching. In this way, an etching stopper side wall film 109of CVD silicon nitride may remain on a region that may cover the sidesurfaces of anti-oxidizing film 106, side surface oxide film 107, andcap film 105.

[0075] Referring now to FIG. 6(a), silicon substrate 101 may then be ionimplanted with an impurity at a high concentration with a self-alignmentmethod using gate electrode 100 and etching stopper side wall film 109as a mask. In this way, source/drain regions 108 may be formed.

[0076] Referring now to FIG. 6(b), interlayer insulating film 110 may beformed over the entire surface to cover gate electrode 100. Interlayerinsulating film may be a BPSG film. A mask (not shown) may be formedhaving an opening over a region corresponding to a source/drain region108. Interlayer insulating film 110 may then be etched to form contacthole 112. When the forming of contact hole 112, a selective etchingprocess for oxide film may be performed under conditions of selectiveetching ratio of the BPSG as interlayer insulating film 110 and siliconnitride as etching stopper side wall film 109. In this way, onlyinterlayer insulating film 110 may be etched without significantlyetching the etching stopper side wall film 109.

[0077] Also, gate insulating film 102 comprising silicon oxide at thebottom surface of contact hole 112 may be etched. In this way, contacthole 112 may be formed with a SAC method and silicon substrate 101including source/drain region 108 may be exposed. Accordingly, with theSAC method, even if the opening in the mask is out of position, upperand lower layer electrodes (104 and 103) may be prevented from beingexposed in contact hole 112 during the formation of contact hole 112 dueto the etching stopper side wall film 109.

[0078] Referring now to FIG. 6(c), polysilicon doped with an impuritymay be formed on interlayer insulating film 110 including contact hole112. Polysilicon may be patterned and etched with a mask (not shown) toform a wiring electrode 113. Wiring electrode 113 may include a contactelectrode 113 a formed in contact hole 112. In this way, contactelectrode 113 a may provide an electrical connection between sourcedrain region 108 of an insulated gate field effect transistor (IGFET)and wiring electrode 113. The IGFET formed may be a LDD type metal oxidesemiconductor field effect transistor (MOSFET), as just one example.

[0079] In the semiconductor device including an IGFET as mentionedabove, the furnace nitriding and the furnace oxidizing may be performedto form anti-oxidizing film 106 and side surface oxide film 107, whichmay be different than the first embodiment. However, similar to thefirst embodiment, side surface oxide film 107 on the side surface oflower layer electrode 103 may protrude from the side of lower layerelectrode 103 by its own thickness farther than anti-oxidizing film 106from the side surface of upper layer electrode 104. Because the sidesurface of upper layer electrode 104 may be covered with anti-oxidizingfilm 106, the side surface of upper layer electrode may not be oxidizedduring the furnace oxidization. In this way, the overhang state in whichthe side surface of upper layer electrode 104 protrudes beyond the sidesurface of lower layer electrode 103 may be prevented.

[0080] Accordingly, when LDD region 114 is formed by ion implantation ofimpurity under self-alignment with the upper layer electrode 104, lowerlayer electrode 103, and anti-oxidizing film 106 and/or side surfaceoxide film 107, no portion of the desired LDD region 114 in the vicinityof the gate electrode may be shielded so that ions may be prevented frombeing implanted. Thus, the impurity diffusion resistance of the LDDregion 114 in the vicinity of gate electrode may be prevented fromincreasing. Also, when BPSG interlayer insulating film 110 is formedafter CVD silicon nitride etching stopper side wall film 109 that coversgate electrode 100 is formed, a void may not occur in a region close tothe gate electrode 100. Even when contact hole 112 and contact electrode113 a are formed, wiring isolation properties of interlayer insulatingfilm 110 may be prevented from suffering adverse affects due to unwantedvoids in filling regions. In this way, characteristics of the IGFETformed may be prevented from being adversely affected.

[0081] In the second embodiment, when cap film 105 is formed withsilicon oxide, cap film 105 may be etched if a mask for the contact holeis out of position. Thus, it may be necessary to form cap film 105 withsilicon nitride or a material having a selective etching ratio forsilicon oxide.

[0082] A third embodiment of the present invention will now be describedwith reference to FIGS. 7 and 8. The third embodiment is an examplewhere the present invention may be applied to an IGFET included in amemory cell and an IGFET in a peripheral circuit. The IGFETs may be MOStransistors, as just one example. Constituents in the second embodimentthat are similar to constituents in the first embodiment may be giventhe same general reference character.

[0083] Referring now to FIG. 7(a), semiconductor memory may include amemory cell region SA and a peripheral region SB defined on a substrate101. Gate electrodes (100A and 100B) of respective IGFETs may be formedin the respective regions in a similar manner as the process of thefirst embodiment illustrated in FIG. 1(a) to FIG. 2(b). In therespective gate electrodes (100A and 100B), anti-oxidizing film 106 maybe formed on side surfaces of cap film 105 and upper layer electrode104. Side surface oxide film 107 may be formed on the side surface oflower layer electrode 103.

[0084] Referring now to FIG. 7(b), peripheral circuit region SB may becovered with mask 120, for example photoresist. Memory cell region SAmay then be ion implanted with an impurity at high concentration. Thus,source/drain region 108A may be formed. In this way, an IGFET in amemory cell may be formed in memory cell region SA.

[0085] Next, as illustrated in FIG. 7(c), mask 120 may be removed andmemory cell region SA may be covered with mask 121, for examplephotoresist. Peripheral circuit region SB may then be ion implanted withan impurity at a low concentration to form LDD region 114B.

[0086] Referring now to FIG. 8(a), mask 121 may be removed and siliconnitride film 109 may be formed over the entire surface with a CVD methodto cover upper surfaces and side surfaces of gate electrodes (100A and100B). Silicon nitride film 109 may be an etching stopper film. CVDsilicon nitride film 109 may be subjected to anisotropic etching. Inthis way, an etching stopper film 109 of CVD silicon nitride may remainon a region that may cover the side surfaces of anti-oxidizing film 106,side surface oxide film 107, cap film 105, and lower electrode 103.

[0087] Referring now to FIG. 8(b), a silicon oxide film 115 may beformed over the entire surface using a CVD method to cover gateelectrodes (100A and 100B) and etching stopper film 109. CVD siliconoxide film 115 may then be subjected to anisotropic etching so that sidewall film 115 may remain on the side surface of etching stopper film109. Etching stopper film 109 may have a thickness of about 30 nm, whichmay be thinner than the etching stopper film of the first embodiment oretching stopper side wall film of the second embodiment. Side wall film115 may be thus formed and may have a thickness of about 20 nm.

[0088] Referring now to FIG. 8(c), memory cell region SA may be coveredwith mask 122, for example photoresist. Peripheral circuit region SB maythen be ion implanted with an impurity at a high concentration with aself-alignment method using gate electrode 100B, etching stopper film109, and side wall film 115 as a mask. In this way, source/drain regions108B may be formed. Thus, an IGFET having a relatively high operatingvoltage LDD structure may be formed. An interval between gate electrode100B and source drain/region 108B (i.e. the size of LDD region 114B) maybe the sum of film thicknesses of etching stopper film 109 and side wallfilm 115.

[0089] Referring now to FIG. 8(d), mask 122 may be removed. Interlayerinsulating film 110 may be formed over the entire surface to cover gateelectrodes (100A and 100B) and provide a flat surface. Interlayerinsulating film 110 may be a BPSG film. A mask may be formed having anopening over a region corresponding to a source/drain regions (108A and108B). Interlayer insulating film 110 may then be etched to form contactholes 112. When the forming of contact holes 112, a selective etchingprocess for oxide film may be performed under conditions of selectiveetching ratio of the BPSG as interlayer insulating film 110 and siliconnitride as etching stopper film 109. Thus, only interlayer insulatingfilm 110 may be etched without significantly etching the etching stopperfilm 109. In this way, contact hole 112 may be formed with a SAC methodand silicon substrate 101 including source/drain regions (108A and 108B)of the respective IGFETs in memory cell region SA and peripheral regionSB may be exposed.

[0090] Even if side wall film 115 is etched when the mask is out ofposition, etching stopper film 109 may inhibit etching so thatrespective upper layer electrodes 104 and lower layer electrodes 103 ofgate electrodes (100A and 100B) may be prevented from being exposed incontact hole 112.

[0091] Thereafter and similarly in other embodiments, a desired patternof conductive material, such as aluminum, may be formed on interlayerinsulating film 110 using a sputtering method or the like. A mask andphotolithography step may then be performed to obtain wiring electrode113. A portion of wiring electrode 113 may form contact electrode 113 a.A contact electrode 113 a may be electrically connected to a sourcedrain region 108A of an IGFET (such as a MOS transistor) included in amemory cell in a memory cell region SA through a contact hole 112. Also,a contact electrode 113 a may be electrically connected to asource/drain region 108B of an LDD type IGFET (such as an LDD type MOStransistor) in peripheral region SB through a contact hole 112.

[0092] In the semiconductor device as described in the third embodiment,side surface oxide film 107 on the side surface of lower layer electrode103 may protrude from the side of lower layer electrode 103 by its ownthickness farther than anti-oxidizing film 106 from the side surface ofupper layer electrode 104. Because the side surface of upper layerelectrode 104 may be covered with anti-oxidizing film 106, the sidesurface of upper layer electrode may not be oxidized. In this way, theoverhang state in which the side surface of upper layer electrode 104protrudes beyond the side surface of lower layer electrode 103 may beprevented.

[0093] Accordingly, when source/drain region 108A is formed in memorycell region SA and LDD region 114B is formed in peripheral circuitregion SB by ion implantation of impurity under self-alignment with thegate electrodes (100A and 100B), no portion of the desired source/drainregion 108A or LDD region 114B in the vicinity of the gate electrodes(100A and 100B) may be shielded so that ions may be prevented from beingimplanted. Thus, the impurity diffusion resistances of the source/drainregion 108A and LDD region 114B in the vicinity of gate electrodes (100Aand 100B) may be prevented from increasing. Also, when interlayerinsulating film 110 is formed after etching stopper side film 109 andside wall film 115 that covers gate electrodes (100A and 100B) isformed, a void may not occur in a region close to the gate electrodes(100A and 100B). Even when contact hole 112 and contact electrode 113 aare formed, wiring isolation properties of interlayer insulating film110 may be prevented from suffering adverse affects due to unwantedvoids in filling regions. In this way, characteristics of the IGFETformed may be prevented from being adversely affected.

[0094] In the third embodiment, the amount of offset between an edge ofLDD region 114B and an edge of source/drain region 108B in an IGFET inthe peripheral circuit region SB may be about 50 nm, which isessentially the sum of thickness of etching stopper film 109 and sidewall film 115. This may provide an IGFET having a sufficiently highoperating voltage characteristics similarly to the first and secondembodiments. Because the LDD structure may be formed using a laminatedstructure of etching stopper film 109 and side wall film 115, etchingstopper film 109 may be formed having a smaller thickness than the firstand second embodiments. Even if the distance between gate electrodes ofan IGFET in memory cell region SA is made smaller, it may be possible toform a sufficient etching stopper film 109 in the IGFET. Even if such areduced spacing is used, the size of contact hole 112 may be made equalto the spacing of adjacent etching stopper films 109 by etchinginterlayer insulating film 110 and side wall film 115 to etching stopperfilm 109 when contact hole 112 is formed to provide an opening tosource/drain region 108A of an IGFET in memory cell region SA. In thisway, the resistance of contact electrode 113A may not increase.

[0095] Although in the embodiments described above, examples including agate electrode having an upper layer electrode constructed with WSi aredisclosed, it may be possible to construct the upper layer electrodewith, for example, another metal silicide having a high melting point.Also, it the upper layer electrode may be constructed with a metal suchas tungsten (W), for example.

[0096] The present invention discloses a structure including a gateelectrode of an IGFET (such as a MOS transistor) where a thermal nitridefilm may be formed on the side surface of upper layer electrode,thereafter the lower layer electrode may be formed using self-alignmentwith the upper layer electrode and the thermal nitride film. The thermaloxide film may be formed on the side surface of the lower layerelectrode. In this way, the side surface of the lower electrode may beformed essentially in alignment with the side surface of the thermalnitride film. Thus, the thermal oxide film on the side surface of thelower layer electrode may protrude by essentially its own thicknessfurther than the thermal nitride film on the side surface of the upperlayer electrode.

[0097] The side surface of the upper layer electrode may be covered withthe thermal nitride film. Thus, the side surface of the upper layerelectrode may not be oxidized when the thermal oxide film is formed. Inthis way, the side surface of the upper layer electrode may be preventedfrom protruding further than the side surface of the lower layerelectrode. Accordingly, portions of the desired source/drain region maynot be shielded so that ions may be prevented from being implanted whenforming the impurity diffusion layer in self-alignment with the gateelectrode. Thus, the impurity diffusion resistance in the vicinity ofthe gate electrode may be prevented from increasing and operatingcharacteristics of the IGFET (for example, MOS transistor) may beprevented from being adversely affected.

[0098] When the interlayer insulating film is formed after the etchingstopper film is formed (for example, with a CVD method) to cover thegate electrode, a void may not occur in a region close to gateelectrodes. Thus, wiring isolation properties of the interlayerinsulating film may be prevented from suffering adverse affects due toundesired voids in filling region. In this way, defects in thesemiconductor device may be reduced.

[0099] It is understood that the embodiments described above areexemplary and the present invention should not be limited to thoseembodiments. Specific structures should not be limited to the describedembodiments.

[0100] Thus, while the various particular embodiments set forth hereinhave been described in detail, the present invention could be subject tovarious changes, substitutions, and alterations without departing fromthe spirit and scope of the invention. Accordingly, the presentinvention is intended to be limited only as defined by the appendedclaims.

What is claimed is:
 1. A semiconductor device including an insulatedgate field effect transistor (IGFET), comprising: a gate electrode ofthe IGFET having a lower layer electrode formed on a gate insulatingfilm and an upper layer electrode formed on the lower layer electrode; acap film formed on the upper layer electrode; a first nitride film on aside surface of the upper layer electrode; an oxide film on a sidesurface of the lower layer electrode; and an etching stopper filmincluding a second nitride film formed on the outside of the firstnitride film and oxide film.
 2. The semiconductor device according toclaim 1, wherein: first nitride film is a thermal nitride film.
 3. Thesemiconductor device of claim 2, wherein: first nitride film is arapidly heated thermal nitride film.
 4. The semiconductor device ofclaim 2, wherein: the first nitride film has a film thickness ofapproximately 2 to 5 nm.
 5. The semiconductor device of claim 2, furtherincluding: an interlayer insulating film formed to cover the gateelectrode of the IGFET; a contact hole opened in the interlayerinsulating film to expose a source/drain region of the IGFET; and aconductor filling the contact hole and electrically connected with thesource/drain region.
 6. The semiconductor device of claim 2, wherein:the oxide film is a thermal oxide film.
 7. The semiconductor device ofclaim 2, wherein: the second nitride film is formed with chemical vapordeposition (CVD).
 8. A method for manufacturing a semiconductor deviceincluding an insulated gate field effect transistor (IGFET), comprisingthe steps of: forming a gate insulating film on a semiconductorsubstrate; forming a laminate film on the gate insulating film, thelaminate film including an insulating film formed on a second conductivefilm formed on a first conductive film; etching the insulating film andsecond conductive film into a predetermined pattern to form a cap filmand an upper layer gate electrode; forming a first nitride film on theside surface of the upper layer gate electrode; etching the firstconductive film using the cap layer, upper layer gate electrode, and thenitride film as a mask to form a lower layer gate electrode; forming afirst oxide film on the side surface of the lower layer electrode; andforming an etching stopper film including a second nitride film over theentire surface.
 9. The method for manufacturing a semiconductor deviceof claim 8, wherein: the first conductive film includes a polysiliconfilm; and the second conductive film includes a metal film.
 10. Themethod for manufacturing a semiconductor device of claim 8, wherein: thefirst conductive film includes a polysilicon film; and the secondconductive film includes a metal silicide film having a high meltingpoint.
 11. The method for manufacturing a semiconductor device of claim8, wherein the first nitride film is a thermal nitride film; and thefirst oxide film is a thermal oxide film.
 12. The method formanufacturing a semiconductor device of claim 8, wherein: forming theetching stopper film includes forming the second nitride film with achemical vapor deposition.
 13. The method for manufacturing asemiconductor device of claim 8, wherein: the first nitride film is athermal nitride film formed with a rapid thermal nitridation step usinga lamp as a heat source.
 14. The method for manufacturing asemiconductor device of claim 8, further including the steps of: forminga source/drain region by doping an impurity into the semiconductorsubstrate after the step of forming the first oxide film; and forming aninterlayer insulating film over the entire surface and selectivelyetching the interlayer insulating film with a selective etching ratiofor the etching stopper film to open a contact hole after the step offorming the etching stopper film.
 15. The method for manufacturing asemiconductor device of claim 8, further including the steps of: forminga LDD (lightly doped drain) region by doping a first impurityconcentration into the semiconductor substrate after the step of formingthe first oxide film; anisotropic etching the etching stopper film toform a side wall etching stopper film on side surfaces of the lowerlayer gate electrode, upper layer gate electrode and cap layer; andforming a source/drain region by doping a second impurity concentrationinto the semiconductor substrate using the side wall etching stopperfilm as a mask wherein the first impurity concentration is lower thanthe second impurity concentration.
 16. The method for manufacturing asemiconductor device of claim 15, further including the steps of:forming a second oxide film over the entire surface of the substratewith a chemical vapor deposition method; anisotropic etching the secondoxide film to form a side oxide film on the side surface of the etchingstopper film; and forming the source/drain region after the step offorming the side wall.
 17. A semiconductor device including a firstregion and a second region, comprising: a first gate electrode of afirst IGFET in the first region having a first lower layer electrodeformed on a first gate insulating film and a first upper layer electrodeformed on the first lower layer electrode; a first cap film formed onthe first upper layer electrode; a first nitride film on a side surfaceof the first upper layer electrode; a first oxide film on a side surfaceof the first lower layer electrode; a first etching stopper filmincluding a second nitride film formed on the outside of the firstnitride film and first oxide film; a second gate electrode of a secondIGFET in the second region having a second lower layer electrode formedon a second gate insulating film and a second upper layer electrodeformed on the second lower layer electrode; a second cap film formed onthe second upper layer electrode; a third nitride film on a side surfaceof the second upper layer electrode; a second oxide film on a sidesurface of the second lower layer electrode; a second etching stopperfilm including a fourth nitride film formed on the outside of the thirdnitride film and second oxide film; and wherein the first IGFET includesa lightly doped drain.
 18. The semiconductor device of claim 17,wherein: the semiconductor device is a semiconductor memory device. 19.The semiconductor device of claim 18, wherein: the first region is amemory cell region and the second region is a peripheral circuit region.20. The semiconductor device of claim 19, further including: a firstcontact providing an electrical connection to a first source/drainregion of the first IGFET; a second contact providing an electricalconnection to a second source/drain region of the second IGFET; and afirst spacing from the first contact to the first gate electrode isgreater than a second spacing from the second contact to the second gateelectrode.